Parallel Processing Unit
Our Parallel Processing Unit provides a 100x performance boost to CPUs.
This unprecedented and game-changing performance is possible with Flow Computing’s Parallel Processing Unit that uses several unique and patented key technologies:
- Thick control flow technology
- Cost-efficient synchronization
- True shared caches/memory
We also guarantee full backwards compatibility for all existing code bases and applications.
In addition, our technology enables significant improvements in the future SW development productivity (5x less active code lines).
How is a 100x performance boost possible?
To illustrate how Flow Computing technology works think about two different highways.
The current CPUs have poor parallel processing performance due to challenges with synchronization and coherency. The performance looks like a highway that has constant roadworks and detours.
Flow Computing’s Parallel Processing Unit accelerates all parallel processing – and most of the processing is parallel – by whopping 100x. Thus it looks like a highway where the traffic flows at the maximum speed.
High performance computing that flows
In our Parallel Processing Unit we represent computation as a flow for a simple and intuitive interplay between control and parallelism.
Thick-control-flow (TCF) is our key concept for this.
Thick-control-flow combines homogeneous computations flowing through the same control path into an entity with a single control but multiple data paths, i.e., “a thread with data parallelism”.
- Simplifies programming by keeping parallel parts of the flow synchronous and allocating precisely the right amount of parallelism for different situations.
- Eliminates the replication of control and common parts of the code as the degree of parallelism increases.
- Separates the execution of flow-common Frontend (CPU) and individual parallel Backend operations (Parallel Processing Unit).
Supporting flows in Hardware
For swift Thick-control-flow execution, we couple traditional execution machinery with units designed for efficient parallel computing from the beginning.
- Control and common operations are executed in the frontends, lending the most solutions from current CPUs optimized for low latency.
- Individual parallel operations are processed in the Parallel Processing Unit with multiple backend units optimized for high throughput.
- True synchronous shared memory is supported for parallel operations via a set of patented special techniques.
Parallel Processing Unit for your CPU frontend
To unleash the power of Flow Computing you need:
- Our Parallel Processing Unit acting as a backend, it is parametric and will be fully configurable for your use cases. It includes:
- Matrix of nodes (the number of nodes selectable in design time)
- Nodes featuring a processing unit, shared caches and switch.
- Your multicore CPU acting as a frontend, it will be modified to work with Flow Computing’s Parallel Processing Unit as the backend.
Simplified parallel programming
Programming a Flow Computing system is much easier than that of current multicore CPUs. Think about adding an N-element array B to an N-element array A:
See how Flow Computing performs
Founding team
CEO
The builder of Flow Computing's business
CTO & Chief Architect
The innovator of Flow Computing's technologies
Chief Designer
The implementor of Flow Computing's technologies
Investors
Our research
Scientific publications:
– M. Forsell, S. Nikula, J. Roivainen, V. Leppänen and J. L. Träff, Performance and Programmability Comparison of the Thick Control Flow Architecture and Current Multicore Processors, Journal of Supercomputing 78, 3 (2022), 3152-3183., https://doi.org/10.1007/s11227-021-03985-0.
– M. Forsell, J. Roivainen and J. Träff, Optimizing Memory Access in TCF Processors with Compute-Update Operations, In the Proceedings of 22nd Workshop on Advances in Parallel and Distributed Computational Models (APDCM’20) in conjunction with the 33rd IEEE International Parallel and Distributed Processing Symposium (IPDPS’20), May 18 – 22, 2020, New Orleans, Louisiana, USA.
– M. Forsell, REPLICA Multiprocessor Framework, White Paper, VTT, April 2020.
– M. Forsell, J. Roivainen, V. Leppänen and J. Träff, Supporting Concurrent Memory Access in TCF Processor Architectures, Microprocessors and Microsystems 63, November 2018, 226-236.
– M. Forsell, Flexible Fibering Scheme for Thick Control Flow Processors, In the Proceedings of the 24th Int’l Conf on Parallel and Distributed Processing Techniques and Applications (PDPTA’18), July 30-August 2, 2018, Las Vegas, USA.
– M. Forsell, J. Roivainen, V. Leppänen and J. Träff, Implementation of Multioperations in Thick Control Flow Processors, In the Proceedings of the 20th Workshop on Advances in Parallel and Distributed Computational Models (APDCM’18) in conjunction with the 31st IEEE International Parallel and Distributed Processing Symposium (IPDPS’18), May 21 – 25, 2018, Vancouver, British Columbia, Canada.
– J-M. Mäkelä, M. Forsell and V. Leppänen, Towards a Language Framework for Thick Control Flows, In the Proceedings of the High Level Programming Models and Supporting Environments (HIPS’17) in conjunction with the 31th IEEE International Parallel and Distributed Processing Symposium (IPDPS’17), May 29 – June 2, 2017, Orlando, Florida USA.
– M. Forsell, J. Roivainen and V. Leppänen, The REPLICA on-chip network, In the Proceeding of the 2016 IEEE Nordic Circouts and Systems Conference (NORCAS’16), November 1-2, 2016, Copenhagen, Denmark.
– M. Forsell, J. Roivainen and V. Leppänen, Outline of a Thick Control Flow Architecture, In the Proceedings of the 5th Workshop on Parallel Programming Models Special Edition on Task Parallelism, October 26-28, 2016, Marina del Rey Marriott, Los Angeles, USA.
– M. Forsell, V. Leppänen and M. Penttonen, Cost of Bandwidth-Optimized Sparse Mesh Layouts, In the Proceedings of 13th International Conference on Parallel Computing Technologies (PaCT’15), Lecture Notes in Computer Science (LNCS) 9251, August 31 – September 4, 2015, 375-389.
– M. Forsell and J. Roivainen, REPLICA T7-16-128 – A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor, In the special session on Multicore, Manycore and Distributed systems at the 48th Asilomar Conference on Signals, Systems, and Computers, November 2-5, 2014, Pacific Grove, USA, 1709- 1713.
– M.Forsell and V. Leppänen, An Extended PRAM-NUMA Model of Computation for TCF Programming, International Journal of Networking and Computing 3, 1 (2013), 98-115.
– V. Leppänen, M. Forsell and J-M. Mäkelä, Thick Control Flows: Introduction and Prospects, In the Proceedings of the 2011 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’11), July 18-21, 2011, Las Vegas, USA, 540-546.
– M. Forsell, Architectural differences of efficient sequential and parallel computers, Journal of Systems Architecture 47, 13 (July 2002), 1017-1041.
– M. Forsell, Minimal Pipeline Architecture-an Alternative to Superscalar Architecture, Microprocessors and Microsystems 20, 5 (1996), 277-284.
Our Parallel Processing Unit provides a 100x performance boost over current CPUs.
Career Opportunities
Want to change the processor world?
Join our team of passionate and enthusiastic people, who put excellence, collaboration and trust at the heart of their daily work. We are searching for talented people for our future company in key operations of HW and SW to support our growth and contribute to our success.
You will have an extensive and holistic role in our future product development and will not be boxed-in to a narrow role like in the bigger companies. We are looking for hands-on doers with bright minds who are excited by the future of high-performance CPUs to join our team. Flow Computing is a right fit for you if:
You are calm under pressure
You have a laid-back intensity
You love problem solving
You are focused and passionate
You want to build a world-class product & have fun doing it
Who are we?
Flow Computing’s Parallel Processing Unit boosts the CPU performance with 100x. We are a deep-tech startup developing this unique product we call Parallel Processing Unit (PPU) that will power-up the future high performance CPUs. Parallel Processing Unit is based on our extensive patent portfolio and several years of intensive research. Our newly established company is backed up by the industry-leading investors.
How did we accomplish this?
Flow Computing utilizes a two-level architecture containing parts optimized for low-latency and high-throughput operations. The performance advantage comes from scalable latency tolerance, cost-efficient synchronization and sufficient intercommunication bandwidth. We also guarantee full backwards compatibility for all existing code bases and applications.
Who are we looking for?
You are a talented processor design and implementation expert with proven experience in parallel processor design technologies and related commercial processor design flows and tools such as the implementation of a processor core, memory systems, interconnects and ALUs/FUs, RISC-V, ISA extensions, instruction set simulators, HDL implementations, prototyping and testing.
You demonstrate a track record of leadership, cross-team collaboration, planning, and delivery of high-quality processor designs.
Requirements?
- 8+ years of experience in processor design and CPU architecture (including preferably also some RISC-V experience)
- Strong understanding of IP and SoC design and verification flows and of silicon process technology and its limitations
- Familiarity with CPU trends in the industry as well as best practises
- Strong analytical and problem-solving skills, as well as the ability to think outside of the box
- Effective communication skills to provide strategic direction to our expert teams
- Master of Science or PhD in SoC or semiconductor or similar
- We work in hybrid mode and are thus not picky about which European country you live – you could be based for example in Oulu, Finland or Cambridge, UK.
If you’re looking to get your hands dirty in designing and developing our groundbreaking Parallel Processing Unit powering up the next generation of high-performance CPUs, apply and email to careers@flow-computing.com and we will get back to you right away.
You will have an extensive and holistic role in our future product development and will not be boxed-in to a narrow role like in the bigger companies. We are looking for hands-on doers with bright minds who are excited by the future of high-performance CPUs to join our team. Flow Computing is a right fit for you if:
You are calm under pressure
You have a laid-back intensity
You love problem solving
You are focused and passionate
You want to build a world-class product & have fun doing it
Who are we?
Flow Computing’s Parallel Processing Unit boosts the CPU performance with 100x. We are a deep-tech startup developing this unique product we call Parallel Processing Unit (PPU) that will power-up the future high performance CPUs. Parallel Processing Unit is based on our extensive patent portfolio and several years of intensive research. Our newly established company is backed up by the industry-leading investors.
How did we accomplish this?
Flow Computing utilizes a two-level architecture containing parts optimized for low-latency and high-throughput operations. The performance advantage comes from scalable latency tolerance, cost-efficient synchronization and sufficient intercommunication bandwidth. We also guarantee full backwards compatibility for all existing code bases and applications.
Who are we looking for?
We are looking for an expert compiler and parallel processing specialist with proven experience in compiler, parallel language and SW support technologies and related commercial design flows and tools such as LLVM and Clang for a new architecture, optimizations, run-time/library support, RISC-V, ISA extensions, instruction set simulators, benchmarking and parallel language implementation.
You demonstrate a track record of leadership, cross-team collaboration, planning, and delivery of high-quality compiler products, language designs, SW simulation tools and sample software.
Requirements?
- 8+ years of experience developing compilers
- Familiarity with Hardware Design & Verification
- Deep experience with LLVM, Clang, MLIR Familiarity with compiler concepts such SIMD, MIMD, Advanced Vector Extensions and Heterogeneous computing High-Performance Computing
- You have deep knowledge of computer architectures and a solid understanding of mapping code to hardware instructions
- Experience contributing to the architecture and design of new and existing systems
- Proven track record in building high-performance and fault-tolerant systems
- We work in hybrid mode and are thus not picky about which European country you live – you could be based for example in Oulu, Finland or Cambridge, UK.
If you’re looking to get your hands dirty in designing and developing our groundbreaking Parallel Processing Unit powering up the next generation of high-performance CPUs, apply and send email to careers@flow-computing.com and we will get back to you right away.
Submit your application and CV by email: info(a)flow-computing.com
Contact Us
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FLOW-Computing
- VTT Technical Research Centre of Finland Ltd
- Phone: +358 20 722 111
- Email: info(a)flow-computing.com
- Address: P.O. Box 1000, FI-02044 VTT, Finland
