100x better CPU processing performance & full backwards compatibility with revolutionary processor IP
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Patented revolutionary processor IP
Our CPU accelerator provides a 100x performance boost over current CPUs in general applications. In addition, we enable 5x SW development productivity improvement.
This unprecedented performance is accomplished with our patented technologies:
- Thick control flow technology
- Cost-efficient synchronization
- True shared caches/memory
We also guarantee full backwards compatibility for all existing code bases and applications.
How is a 100x performance boost is possible?
To illustrate how Flow-computing technology works think about two different highways.
Because the current CPUs have poor parallel processing performance due to challenges with synchronization and coherency it would be a highway that has constant roadworks and detours.
Flow-computing CPU accelerator accelerates the parallel processing performance by 100x. Thus it would be a highway where the traffic flows at maximum speed.
Computing that flows
We represent computation as a flow for a simple and intuitive interplay between control and parallelism.
Thick-control-flow (TCF) is our key concept for this.
Thick-control-flow combines homogeneous computations flowing through the same control path into an entity with a single control but multiple data paths, i.e., “a thread with data parallelism”.
- Simplifies programming by keeping parallel parts of the flow synchronous and allocating precisely the right amount of parallelism for different situations.
- Eliminates the replication of control and common parts of the code as the degree of parallelism increases.
- Separates the execution of flow-common Frontend and individual parallel Backend operations.
Supporting flows in Hardware
For swift Thick-control-flow execution, we couple traditional execution machinery with units designed for efficient parallel computing from the beginning.
- Control and common operations are executed in the frontends, lending the most solutions from current CPUs optimized for low latency.
- Individual parallel operations are processed in the backend units optimized for high throughput.
- True synchronous shared memory is supported for parallel operations via a set of patented special techniques.
Accelerator for your CPU frontend
To unleash the power of Flow-computing you need:
- Our backend IP will be configured for your use cases. It includes:
- Matrix of nodes (the number of nodes selectable in design time)
- Nodes featuring a processing unit, shared caches and switch.
- Your multicore frontend to be modified to work with the backend.
Simplified parallel programming
Programming a Flow-computing system is much easier than that of current multicore CPUs. Think about adding an N-element array B to an N-element array A:
See how Flow-computing performs
Founding team
Chief Businessman
Builder of new businesses, start-ups, ventures and spin-offs.
Chief Architect
Processor architecture, methodology and the theory behind the technology.
Chief Designer
HDL modeling, synthesis, implementation and testing.
Investors
Our research
Scientific publications:
– M. Forsell, S. Nikula, J. Roivainen, V. Leppänen and J. L. Träff, Performance and Programmability Comparison of the Thick Control Flow Architecture and Current Multicore Processors, Journal of Supercomputing 78, 3 (2022), 3152-3183., https://doi.org/10.1007/s11227-021-03985-0.
– M. Forsell, J. Roivainen and J. Träff, Optimizing Memory Access in TCF Processors with Compute-Update Operations, In the Proceedings of 22nd Workshop on Advances in Parallel and Distributed Computational Models (APDCM’20) in conjunction with the 33rd IEEE International Parallel and Distributed Processing Symposium (IPDPS’20), May 18 – 22, 2020, New Orleans, Louisiana, USA.
– M. Forsell, REPLICA Multiprocessor Framework, White Paper, VTT, April 2020.
– M. Forsell, J. Roivainen, V. Leppänen and J. Träff, Supporting Concurrent Memory Access in TCF Processor Architectures, Microprocessors and Microsystems 63, November 2018, 226-236.
– M. Forsell, Flexible Fibering Scheme for Thick Control Flow Processors, In the Proceedings of the 24th Int’l Conf on Parallel and Distributed Processing Techniques and Applications (PDPTA’18), July 30-August 2, 2018, Las Vegas, USA.
– M. Forsell, J. Roivainen, V. Leppänen and J. Träff, Implementation of Multioperations in Thick Control Flow Processors, In the Proceedings of the 20th Workshop on Advances in Parallel and Distributed Computational Models (APDCM’18) in conjunction with the 31st IEEE International Parallel and Distributed Processing Symposium (IPDPS’18), May 21 – 25, 2018, Vancouver, British Columbia, Canada.
– J-M. Mäkelä, M. Forsell and V. Leppänen, Towards a Language Framework for Thick Control Flows, In the Proceedings of the High Level Programming Models and Supporting Environments (HIPS’17) in conjunction with the 31th IEEE International Parallel and Distributed Processing Symposium (IPDPS’17), May 29 – June 2, 2017, Orlando, Florida USA.
– M. Forsell, J. Roivainen and V. Leppänen, The REPLICA on-chip network, In the Proceeding of the 2016 IEEE Nordic Circouts and Systems Conference (NORCAS’16), November 1-2, 2016, Copenhagen, Denmark.
– M. Forsell, J. Roivainen and V. Leppänen, Outline of a Thick Control Flow Architecture, In the Proceedings of the 5th Workshop on Parallel Programming Models Special Edition on Task Parallelism, October 26-28, 2016, Marina del Rey Marriott, Los Angeles, USA.
– M. Forsell, V. Leppänen and M. Penttonen, Cost of Bandwidth-Optimized Sparse Mesh Layouts, In the Proceedings of 13th International Conference on Parallel Computing Technologies (PaCT’15), Lecture Notes in Computer Science (LNCS) 9251, August 31 – September 4, 2015, 375-389.
– M. Forsell and J. Roivainen, REPLICA T7-16-128 – A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor, In the special session on Multicore, Manycore and Distributed systems at the 48th Asilomar Conference on Signals, Systems, and Computers, November 2-5, 2014, Pacific Grove, USA, 1709- 1713.
– M.Forsell and V. Leppänen, An Extended PRAM-NUMA Model of Computation for TCF Programming, International Journal of Networking and Computing 3, 1 (2013), 98-115.
– V. Leppänen, M. Forsell and J-M. Mäkelä, Thick Control Flows: Introduction and Prospects, In the Proceedings of the 2011 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’11), July 18-21, 2011, Las Vegas, USA, 540-546.
– M. Forsell, Architectural differences of efficient sequential and parallel computers, Journal of Systems Architecture 47, 13 (July 2002), 1017-1041.
– M. Forsell, Minimal Pipeline Architecture-an Alternative to Superscalar Architecture, Microprocessors and Microsystems 20, 5 (1996), 277-284.
Our technology provides a 100x performance boost over current CPUs. In addition, we enable 5x SW development productivity improvement.
Career Opportunities
Want to change the processor world?
Join our team of passionate and enthusiastic people, who put excellence, collaboration and trust at the heart of their daily work. We are searching for talented people for our future company in key operations of HW and SW to support our growth and contribute to our success.
You are a talented processor design and implementation expert with proven experience in parallel processor design technologies and related commercial processor design flows and tools such as the implementation of a processor core, memory systems, interconnects and ALUs/FUs, RISC-V, ISA extensions, instruction set simulators, HDL implementations, prototyping and testing. You demonstrate a track record of leadership, cross-team collaboration, planning, and delivery of high-quality processor designs.
You are a strong compiler and parallel processing specialist with proven experience in compiler, parallel language and SW support technologies and related commercial design flows and tools such as LLVM for a new architecture, optimizations, run-time/library support, RISC-V, ISA extensions, instruction set simulators, benchmarking and parallel language implementation. You demonstrate a track record of leadership, cross-team collaboration, planning, and delivery of high-quality compiler products, language designs, SW simulation tools and sample software.
Are you interested to work with multicore processor design/implementation and parallel software methodology/tools? Do you feel that you would be an important add-on to our team in turning Flow-computing into a success story?
Send us your open application and CV.
Submit your application and CV by email: info(a)flow-computing.com
Contact Us
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FLOW-Computing
- VTT Technical Research Centre of Finland Ltd
- Phone: +358 20 722 111
- Email: info(a)flow-computing.com
- Address: P.O. Box 1000, FI-02044 VTT, Finland
