Hot Chips 2026: What IBM’s dual-architecture processor tells us about the future of CPU architecture

At Hot Chips 2026, IBM Distinguished Engineer Dr. Christian Zoellin presented the future IBM Z and LinuxONE processor and AI inference acceleration chipset. The processor supports two instruction set architectures: IBM Z and Arm.

The presentation raises an interesting question about where CPU architecture is heading: does the future really require choosing one ISA, or can different architectures coexist and contribute capabilities suited to different workloads and ecosystems?

Multiple ecosystems. One processor.

During the Q&A, Dr. Zoellin explained that IBM already had generations of very high-frequency processor cores and added Arm support to this existing foundation. When asked why IBM chose Arm, he pointed to the breadth of the Arm software ecosystem and the wide range of use cases it supports.

The integration goes deeper than simply placing two architectures next to each other. IBM's simultaneous multithreading capabilities remain available, while individual threads can independently switch between Z and Arm execution modes. The two modes therefore share underlying processor resources.

IBM's approach challenges the idea that the future of CPU architecture has to converge around a single instruction set. Z and Arm serve different ecosystems and use cases, yet IBM has designed them to coexist within the same processor.

The more interesting question may therefore be less about which ISA ultimately “wins” and more about how different architectures can contribute capabilities suited to different workloads.

This also fits a broader trend discussed around Hot Chips. In Computerworld's analysis of the event, industry analysts described computing infrastructure as becoming increasingly heterogeneous, with CPUs, GPUs and specialized processors working together as system architectures evolve.

CPU + the right architecture for the workload

This is particularly interesting from our perspective because the Parallel Processing Unit® (Flow PPU) is part of heterogeneous computing infrastructure and is designed to be instruction-set independent.

Rather than requiring a particular CPU ISA, Flow PPU can complement architectures including Arm, x86, RISC-V and Power/OpenPOWER, adding a closely coupled architecture for scalable general-purpose parallel computation alongside the CPU.

The CPU continues handling sequential execution, control and existing software, while suitable parallel sections can execute on Flow PPU. Both access unified memory.

In other words, the choice of CPU ecosystem and the choice to add parallel acceleration do not have to be the same architectural decision.

IBM and Flow approach CPU architecture from complementary directions. IBM is expanding the capabilities and software ecosystems supported by its CPU platform. Flow adds another capability alongside the CPU: closely coupled parallel acceleration for workloads where scalable general-purpose parallel processing can add value.

The broader direction is CPU + the right architecture for each workload. IBM’s dual-ISA approach shows how multiple instruction-set ecosystems can coexist within a CPU platform. Flow’s ISA-independent approach means parallel acceleration can complement different CPU ecosystems rather than requiring one particular ISA.

The future of CPU performance may be less about choosing one architecture to do everything, and more about combining complementary architectures for the workloads they serve best.

See what parallel CPU acceleration can deliver in our performance results.