Hot Chips 2026: Intel Diamond Rapids and the Challenge of Scaling to 256 CPU Cores

At Hot Chips 2026, Intel presented Diamond Rapids, its next-generation Xeon CPU, designed around a simple but increasingly difficult challenge: how do you continue scaling CPU performance as data-center processors grow to hundreds of cores?

Intel framed evolving data-center workloads around performance, efficiency, acceleration and scalability, arguing that the next frontier of CPU architecture depends on how effectively processors can move and process data at hyperscale.

Diamond Rapids pushes that scale considerably. The SoC supports up to 256 performance cores, up to 1.28 GB of last-level cache, 16 memory channels and 128 lanes supporting PCIe Gen6, CXL 3.0 and UPI 3.

But the interesting part isn't simply the number of cores. It's the architecture Intel has built around them.

More cores require more scalable architecture

Diamond Rapids uses scalable compute building blocks connected through a unified memory fabric and fabric hubs. Intel specifies a memory subsystem capable of up to 1.6 TB/s of bandwidth.

The Hot Chips Q&A reinforced how important this surrounding architecture becomes at scale.

Intel repeatedly emphasized latency, bandwidth and uniformity when explaining its design decisions. In discussing the connections between compute building blocks and fabric hubs, the presenter explained that avoiding additional hops helps provide more uniform latency across the processor. The architecture was ultimately designed to provide uniform memory latency and bandwidth across a large number of high-performance cores.

Intel has also moved its snoop-filter directory on-die, which it says reduces latency and coherence traffic for cache lookups.

These are reminders that scaling CPU performance isn't simply a matter of adding more cores. The architecture around those cores has to scale with them.

Industry analysis is increasingly making the same point. Computerworld highlighted analyst observations that data movement is becoming a major system-level bottleneck, pushing architects to rethink where and how computation happens.

A complementary approach to CPU scalability

This is where Diamond Rapids becomes particularly interesting from Flow's perspective.

Traditional multicore architectures can encounter increasing overhead from memory access, synchronization and cache coherence as parallel workloads scale. We approach these challenges by adding a closely coupled Parallel Processing Unit® (Flow PPU) alongside conventional CPU cores.

The CPU continues handling sequential execution, control and existing software, while suitable general-purpose parallel sections can execute on Flow PPU.

The goal isn't to replace architectures such as Xeon. It's to extend the parallel performance available to CPU-powered systems.

Flow's performance modeling illustrates the potential. Against a 72-core 6th Gen Intel Xeon reference processor, a modeled high-end 256-core Flow PPU showed speedup potential of approximately 36× for compute-heavy workloads, 171× for memory-heavy workloads and 15,700× for synchronization-heavy workloads.

These results aren't measurements of Diamond Rapids itself. Instead, they illustrate something particularly relevant as server CPUs scale toward hundreds of cores: different workload characteristics create very different scaling challenges.

Scaling beyond core count

Diamond Rapids demonstrates just how much engineering is required to make a 256-core CPU system work efficiently, from 3D packaging and scalable compute building blocks to cache coherency, memory bandwidth and fabric architecture.

Flow approaches the same broader challenge from a complementary direction: adding scalable parallel execution capabilities alongside the CPU.

As CPU core counts continue growing, the next generation of performance may depend not only on how many cores fit inside a processor, but on how effectively the entire architecture allows parallel workloads to scale.

Explore Flow's architecture and latest performance results: Flow PPU Performance